Complex FPGA verification methodology

Hi,

Welcome to Intel community!

Generally VHDL, Verilog, System Verilog languages are used for verification but for verification of huge & complex designs verification methodologies are recommended, for example OVM, UVM etc.

To use these methodologies, user must have knowledge of all languages, methodologies & simulation tools. Since you are newbie in verification & familiar only with VHDL, I would like to suggest with Quartus tool,

1) Will writing only the testbench for the top level design help, or should I verify each and every schematic individually by writing testbench to each of them.

-> If you are using pre-verified schematics then you can directly write test bench for top level design else need to verify each & every module. you can use waveform editor : https://www.youtube.com/watch?v=a8JAkKhxlQI

2) Should I use System verilog(or other languages) for writing testbench, or writing them in VHDL is fine? I have experience of writing testbenches only in VHDL.

-> Since you are experience with VHDL, make use of VHDL or waveform editor. If you want explore the verilog, system verilog please go through the 'Fundamental Par 1 & 2' online free Intel training : https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html

3) Kindly provide link to any resource or guides which could help me in this verification task in Quartus Prime.

-> you can use waveform editor, simulation using Native Link & just go through the Intel online training : https://www.youtube.com/watch?v=PmVVXQchv2c

Regards,

Vicky