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Hi Kaz,
I have tested the altddio_out megacore on my design but I have still a problem in getting it to work as expected. I have had a look into the megacore manual, and I saw that this block would do exactly what I would like to do, but when I simulate it in Model-Sim I just cannot see the DDR behavior.
Basically I have two counters in my testbench, counting with the same clock period, so once they pass throught the altddio_out block, I should see in output a dual data rate signal, but this seems not happening. What could it depend on?
I will try to follow a basic tutorial on the altddio_out megacore, but I think I´m using the block correctly.
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make one counter start from 0 and increment by 2 (0,2,4,...)
set other counter to start at 1 and increment by 2(1,3,5...) then the ddr output should be 0,1,2,3,4... assuming you feed the pair in that sense
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