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Your edge interleaver(DDR) can be done readily using altddrio_out. There is no reason to design your own unless you know what you are doing.
You pass cos data and sin data in parallel into altddrio_out together with their clock and you are done.
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Hi Kaz,
I have tested the altddio_out megacore on my design but I have still a problem in getting it to work as expected. I have had a look into the megacore manual, and I saw that this block would do exactly what I would like to do, but when I simulate it in Model-Sim I just cannot see the DDR behavior.
Basically I have two counters in my testbench, counting with the same clock period, so once they pass throught the altddio_out block, I should see in output a dual data rate signal, but this seems not happening. What could it depend on?
I will try to follow a basic tutorial on the altddio_out megacore, but I think I´m using the block correctly.
Honored Contributor
