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Hi Kaz,
I have tried to simulate the sample interleaving thorugh a multiplexer. In order to test if this interleaving is working, I have set up a test bench:
I have two 16 bits counters, driven by a clock signal with 10 ns of period. After this I have my MUX, where the select signal is driven by the same clock which I am using to trigger the counters.
When I simulate this, I see that on each rising edge of the clock, the counters are counting correctly, but the output of my system is just changing with every rising edge of the clock. Normally I would expect that the output of my MUX may change when the selector signal has a logic value of 0., in such a way that during a clock cylce I sent out of my mux two different data in a row.
Am I facing a timing constraint? Such as, my data will really take not less that one clock cycle even if I play around with the select signal of the following MUX?
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Your edge interleaver(DDR) can be done readily using altddrio_out. There is no reason to design your own unless you know what you are doing.
You pass cos data and sin data in parallel into altddrio_out together with their clock and you are done.
Honored Contributor
