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Altera_Forum
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12 years ago

Complex dual tone generation

Hello, I am trying to realize a VHDL code able to generate a complex baseband dual tone signal. What i would like to to is then send this signal through the HSMC port to a DAC evaluation board,...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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Hi Kaz,

thanks for your replies, I have found another point during the development of my testing system which is not really cleart to me. I have implemented my system as I have described at the beginning of this post, but now I have a small problem interfacing my design with my DAC evaluation module.

I don't know if I am doing right on the FPGA side, but basically I want now to play my signal on the HSMC connector by sending the data and the data clock for the evaluation board.

The point is that the generated signal is in baseband, but in order to feed it inside the DAC board, I need to interleave it.

Basically the DAC will accept interleaved LVDS data, I have 16 bits out of my VCO for the sine and cosine components. After the NCO megacore block, I use a multiplexer to implement the data interleave (basically my idea is that when the clock is on the rising edge, I send a 16 bits sample for the sine component and when there is a falling edge I send a sample from the quadrature component).

Now, which one would be the best way to interface this to my DAC evaluation module?

At the beginning I just went to the pin planner, and I have configured each HSMC TX pin as LVDS, then I routed the output of the multiplexer just to the positive pins. As I have read around on the forum, quartus should generate the differential pair automatically....

But...does this mean that I am done when I do so? Or should I use a ALTLVDS_TX megacore after the multiplexer?

The problem is that at the moment I don't have a real way to test if I am actually sending something to the HSMC pins, but would be nice to understand if at least operatively I am doing right.

DO you have any suggestion for me?

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Once you get your interleaved stream(SDR on rising edge only) you then pass it through altddio_out which will convert it to DDR (rising/falling edges) Then you pass it to the pins (you can directly connect to positive pins only or use altlvds). These are two separate steps so don't mix up between them.