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Altera_Forum's avatar
Altera_Forum
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12 years ago

Complete tool for beginners

Hi, i just started learning about VHDL and FPGAs. I have found too many information online and i don't know where to start from. I am wondering if Quartus Web edition and ModelSim is everything i nee...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

A testbench is a VHDL entity you usualy do not intend to synthesise. It will create stimulus for the unit under test, and hence will probably have things that are not suitable for synthesis:

eg:

--clock generator

clk <= not clk after 10 ns; --50MHz clock.