compiling error

You didn't post the declaration of the vector count_b, but I guess:

signal count_b : std_logic_vector(4 downto 0);

you can't add vector of type "std_logic_vector" ( width some library you can do it, but isn't a good practice ). The to do it is:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity.....

architecture...

signal count_b : unsigned(4 downto 0);

process...

count_b <= count_b + 1;

If you need count_b as a std_logic_vector type you may cast it:

count_2 <= std_logic_vector(count_b);

( count_2 is an arbitrary name )

You are mixing types. VHDL cares about the type (integer/vector).

Try:

count_b <= count_b + '1';

It should fix it.

--- Quote Start ---

You are mixing types. VHDL cares about the type (integer/vector).

Try:

count_b <= count_b + '1';

It should fix it.

--- Quote End ---

that wont work with standard VHDL, assuming count_b is a std_logic_vector, because you cannot do arithmatic with std_logic_vectors.

You need to include the numeric_std library and make count_b an unsigned, as bertulus suggested to make the origional code work.

But this is all speculation, because we havent seen all of the OPs code.

I did exactly what Bertulus suggested and it works.

Thanks you all.