compiling error

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You are mixing types. VHDL cares about the type (integer/vector).

Try:

count_b <= count_b + '1';

It should fix it.

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that wont work with standard VHDL, assuming count_b is a std_logic_vector, because you cannot do arithmatic with std_logic_vectors.

You need to include the numeric_std library and make count_b an unsigned, as bertulus suggested to make the origional code work.

But this is all speculation, because we havent seen all of the OPs code.