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PRega1's avatar
PRega1
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6 years ago

Compensating for clock netwrok delay

Hello, I have a design (5CGXFC5C6U19I7) receiving a source synchronous DDR data interface from an ADC. The input clock is connected to a global clock input (CLK6, unfortunately not a DQS). The input ...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello , sorry for late message .. i caught into other stuff...Can I know update on the same ? If you still having the issue can you let me know ?

Thank you ,

Regards,

Sree