Compensating for clock netwrok delay

Hello, clock frequency is 300MHz, or 600MT/s.

Tuning D0/D3 delays in DDIO input pad does not help.

I understand your point and I know that I would be better off if the clock signal was connected to a DQS input. Can the PHYLite work with a global clock instead ? Now rather than waiting for a re-spin of the HW, i am looking for a way to compensate for the clock network. Hence my question.

In "Normal Compensation" mode, I was expecting the PLL to compensate for the delay. However, Quartus introduces a CLKCTRL and a buffer (the clock tree) that are not in the PLL feedback. Is this normal ? Why ? If not, is tehre a way to workaround this ?

Pascal