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PRega1
New Contributor
New ContributorCompensating for clock netwrok delay
Hello, I have a design (5CGXFC5C6U19I7) receiving a source synchronous DDR data interface from an ADC. The input clock is connected to a global clock input (CLK6, unfortunately not a DQS). The input ...
KennyT_altera
Super Contributor
Super Contributorbasically, if you are running more than 200Mhz. You will have to use altdq_dqs.
you can refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_phylite.pdf
