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Altera_Forum
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13 years ago

Comparing two ring oscillators in FPGA for RO PUF

Hi, i'm doing a project on Ring Oscillator PUF to implement on FPGA. In my design, i have compared 2 ROs to see which RO is faster. When the first RO is faster than the second RO, the output b...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Thank you for your reply.

What i meant by unstable was, when i compare both ROs the output is sometimes '1' and sometimes '0'.

For example, when tested the chip 10 times, the chip produced output '1' 6 times and '0' 4 times.

I would like the design to produced only '1' or '0' 9 times when i test it again 10 times.

I use counter to count the frequency of the RO and it is asynchronous. Does this mean that my design is able to compare asynchronous clocks?