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Altera_Forum's avatar
Altera_Forum
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10 years ago

comparing arria10 and stratix v fmax for same design

hi, i have a RTL design which I map to arrai10 and stratix V fpgas. i synthesize the design in synplify_premier for arria10 and stratixV (using the exact same synth settings) and transfer the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Have you tried using Quartus to synthesize your source code, rather than running it through Synplify? I would certainly expect higher Fmax values for Arria 10 over Stratix V.

What speed grade devices are you using from each family for your test?

Having asked those questions - I've just run one of my reference designs (rtl only, no PLLs or other Altera IP) through each family, selecting -2 speed grade in each case. I find the Fmax in each case surprisingly similar, and broadly in line with your findings - Stratix V is reportedly about 0.05% quicker...

I think have a need to try that again with another design...

Cheers,

Alex