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Altera_Forum's avatar
Altera_Forum
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10 years ago

comparing arria10 and stratix v fmax for same design

hi,

i have a RTL design which I map to arrai10 and stratix V fpgas.

i synthesize the design in synplify_premier for arria10 and stratixV (using the exact same synth settings) and transfer the .vqm file to quartusII for mapping and PAR.

i have 3 clocks in my design clk1, clk2, clk3 constrained to 100, 125 and 150MHz.

when i implement the design on arria10, then the clk frequencies achievable come out as follows -

clk1 - fmax = 85MHz

clk2 - fmax = 100.7MHz

clk3 - fmax = 110MHz

however when i map the design on stratixV, then clk frequencies achievable come out as follows -

clk1 - fmax = 107MHz

clk2 - fmax = 117.7MHz

clk3 - fmax = 108MHz

i notice that the clk frequencies are higher for stratixV (28nm) but arria10 is 20 nm. so should the clk frequencies not be higher for arria 10?

what factors could lead to slower clocks on a 20nm FPGA as compared to a 28nm FPGA?

also, can we port the same RTL design from one fpga family to other and expect an improvement in frequency or some redesign is needed?

please help me understand this.

thanks and regards,

zubin kumar.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Have you tried using Quartus to synthesize your source code, rather than running it through Synplify? I would certainly expect higher Fmax values for Arria 10 over Stratix V.

    What speed grade devices are you using from each family for your test?

    Having asked those questions - I've just run one of my reference designs (rtl only, no PLLs or other Altera IP) through each family, selecting -2 speed grade in each case. I find the Fmax in each case surprisingly similar, and broadly in line with your findings - Stratix V is reportedly about 0.05% quicker...

    I think have a need to try that again with another design...

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    hi,

    i am using synplify because there are some for-loop statements which quartus is having issues with and is giving them as syntax errors - "end module found at place ..." . synplify is able to parse them properly.

    is it that to make full use of the arria10 or stratixV fabrics and to get proper speedup, we have to redesign the RTL?

    z.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I would always ask questions of code that one tool understands and another doesn't. I might ask if it should be re-written. However, given the error message - when synthesising with Quartus, are you specifying the right verilog version for your code? Forgive me if it's written in VHDL, but the same applies. Are you simply using a newer language construct that Quartus isn't set to understand. Check what version of the language you've set Quartus to use: 'Assignments' -> 'Settings' -> 'VHDL/Verilog HDL Input' catagories.

    I've just finished another reference design run. This time Arria 10's Fmax is a good 5% grater than Stratix V.

    Cheers,

    Alex