comparing arria10 and stratix v fmax for same design

I would always ask questions of code that one tool understands and another doesn't. I might ask if it should be re-written. However, given the error message - when synthesising with Quartus, are you specifying the right verilog version for your code? Forgive me if it's written in VHDL, but the same applies. Are you simply using a newer language construct that Quartus isn't set to understand. Check what version of the language you've set Quartus to use: 'Assignments' -> 'Settings' -> 'VHDL/Verilog HDL Input' catagories.