Communication between NIOSII core and HDL (Verilog) module- Cyclone IVGX

Question

Though I have some background with programming, it is very less when it comes to understanding hardware specifications and resulting functionalities. Therefore even after going through NIOSII reference handbooks, I have to post this question.

problem. I need to create a working model of a NIOSII core communicating (exchanging data bits) with another sequential HDL module in the FPGA. So I create a NIOSII (block symbol file) with 8bit wide pio(output) and another block symbol file of a Verilog module that accepts 8 bit wide input and stores it in a register.

I then create new project with a Block Diagram file as top level entity and have both the blocks (NIOSII and HDL) connected through a bus .

My question is, is this the desired way of exchanging data for my scenario, or are there any other clever and more efficient means to do so.

PS:Why I haven't tried it on the hardware and checked yet is because I am getting errors while implementing a simple NIOSII on the FPGA which I am dealing with separately. Just want to make sure that my though process for my problem is correct.

altera_forum · Answer

Hi,

a much better way is to use the Altera Avalon Bus.

Have a look at this document:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf

Implementing a memory mapped avalon interface is easy, you can use the PIO as reference design(written in Verilog).

Greets

Olaf

altera_forum · Answer

"Implementing a memory mapped avalon interface is easy, you can use the PIO as reference design(written in Verilog)."

So even with using the avalon interface, I wilil still require PIO's? Or will the Onchip memory data can directly be transferred through avalon bus to the HDL modules.

Thanks

altera_forum · Answer

No, you don´t need PIO´s.

I mean, that you can use the PIO code as reference, to write your own.

Than you can create your own component in QSYS and let it communicate via the Avalon Interface with your NIOSII.

Or you can have a look at this tutorial:

ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/making_qsys_components.pdf

It describes creating custom components in Verilog or VHDL.

I have createt my first component with this tutorial.

Greets

Olaf

altera_forum · Answer

Thanks a lot for your time! Will take that road now!

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Communication between NIOSII core and HDL (Verilog) module- Cyclone IVGX

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