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Altera_Forum's avatar
Altera_Forum
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9 years ago

Communication between NIOSII core and HDL (Verilog) module- Cyclone IVGX

Though I have some background with programming, it is very less when it comes to understanding hardware specifications and resulting functionalities. Therefore even after going through NIOSII referen...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

"Implementing a memory mapped avalon interface is easy, you can use the PIO as reference design(written in Verilog)."

So even with using the avalon interface, I wilil still require PIO's? Or will the Onchip memory data can directly be transferred through avalon bus to the HDL modules.

Thanks