Communication between NIOSII core and HDL (Verilog) module- Cyclone IVGX

Hi,

a much better way is to use the Altera Avalon Bus.

Have a look at this document:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf

Implementing a memory mapped avalon interface is easy, you can use the PIO as reference design(written in Verilog).

Greets

Olaf