Forum Discussion

Honored Contributor

16 years ago

communicatiom between external board running CDR and FPGA

hi all

i need your help please.

communication between external board running CDR and FPGA

I am working in connecting Startix Gx 'EP1SGX40GF1020C5' FPGA with external board .

the board Receive optical signal carrying information at 125 Mbps .

and it convert this signal using CDR to tow line one for data 125 Mbps and the other for clock 125 MHZ.

i need to connect the tow line data and clock to the FPGA using SMA connectors.

could you please give me suggestion how can i solve this problem.

which type of protocol good to use in side the FPGA .

what i have to do if i want to connect directly the optical signal to the FPGA without sing the borad.

Thank you

Altera_Forum
Honored Contributor
16 years ago
The basic point is to perform oversampling of the input data stream to recover the clock in a digital PLL. If the achievable regular design clock frequency isn't high enough, a SERDES circuit can sample the data at a multiple of the design base clock. The SERDES output has to be processed to extract the clock edges and data bits. Alternatively, DDIO cells can be used for a sampling at double design base clock.