communicatiom between external board running CDR and FPGA

The basic point is to perform oversampling of the input data stream to recover the clock in a digital PLL. If the achievable regular design clock frequency isn't high enough, a SERDES circuit can sample the data at a multiple of the design base clock. The SERDES output has to be processed to extract the clock edges and data bits. Alternatively, DDIO cells can be used for a sampling at double design base clock.