communicatiom between external board running CDR and FPGA

You go to megawizard and instantiate it(select the component from the list, possibly called altlvds). then follow the GUI.

ENTITY serdes_rx_core IS
PORT(
        rx_in               : IN STD_LOGIC;   --819.2Mbps
        rx_inclock        : IN STD_LOGIC;   -- 40.96MHz clk for pll
 
        rx_dpa_locked  : OUT STD_LOGIC;
        rx_locked         : OUT STD_LOGIC ;
        rx_out             : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);-- 16:1
        rx_outclock      : OUT STD_LOGIC   -- parallel data clk
 );
END serdes_rx_core;