communicatiom between external board running CDR and FPGA

Actually, I don't see a way to use GX transceiver for lower data rates by upsampling, particularly regarding CDR operation. CDR can be imagined as a PLL locking on the serial input edges, in can't tolerate additional edges introduced by upsampling.

User CDR designs are mostly all digital PLL, involving oversampling of the input data stream by a sufficient factor, e.g. factor 4 as used in full speed USB. It seems still feasible for 125 Mbps in Stratix devices, particularly if DDIO or possibly SERDES circuits are utilized.

Another user CDR option is provided by PLLs with dynamic phase shifting option, as present in newer devices starting with Cyclone III, Stratix III and Arria II.