Combining AS and PS configuration schemes

In my opinion, it can be save. I think, Altera wanted to issue a warning, that an undefined MSEL state during power up can cause inpredictable device behaviour. If you drive MSEL by an Arria, that is typically releasing the power-up reset at the same time as the slave Cyclone FPGAs, you should think about a means as strong pull-up/pull-down resistors or additional drivers to ensure stable MSEL conditions. In any case, you should try yourself, what must be done.