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Altera_Forum
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18 years ago

Combining AS and JTAG configuration schemes

Hi all ! I am a newbie in FPGA field. I am trying to design very simple Cyclone III FPGA board as follows * FPGA : EP3C10E144C7 * VCCIN : 1.2V * VCCD_PLL1,2 : 1.2V * VCCA : 2.5V * VC...
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Altera_Forum
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17 years ago

I'm not an expert on this, but I suspect that as long as the rise in voltage is monotonic, the ramp TIME is not very critical. I think what you want to avoid is having the voltage rise above some level, then dip below some threshold, then rise again to its final value.