Combine PCIE and SGMIIs in QSYS structure Cyclone V

Hi,

The error code state that the reconfiguration controller is removed. This note ties in with the error message which suggests a problem with the PMA_AUX block.

The PMA_AUX block is a physical circuit inside the FPGA that the reconfiguration controller IP must access. For your design to fit, all transceivers must connect to a reconfiguration controller.

One other possibility I can think of here is that you’ve used the PCI Express Design example in your project. It has been a while since I have looked at this design on Cyclone V but I seem to remember that the design example instantiates the reconfiguration controller within the IP. IF you have two reconfiguration controllers trying to access the same transceiver block then this might cause a connection conflict. There is more information about connecting the reconfiguration controller in the V-Series PHY IP userguide.

The chapter name is “Transceiver Reconfiguration Controller to PHY IP Connectivity”

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf

I believe you might be violating figure 17-13.

IF you are using the PCI Express design example, you might need to remove the reconfiguration controller and instantiate a single one outside of the IP that connects to PCI Express blocks.

Regards,

Wincent_Intel