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Majo's avatar
Majo
Icon for New Contributor rankNew Contributor
2 years ago

Combine PCIE and SGMIIs in QSYS structure Cyclone V

Hi, I use PCIE HIP in Cyclone V wrapped into QSYS structure. Is it possible to add multiple (3 ports) of TRI Ethernet (SGMII) IPs to this existed PCIE QSYS structure? I have succeeded to add only 1 ...
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi


Please refer to the C5 Transceiver datasheet , the PCIe x1 will take up 2 channel for the placement , this is the limitation for the device itself , this means only one PCIe and one SGMII is possible for your solution , thanks


Regards,

Wincent_Intel


Majo's avatar
Majo
Icon for New Contributor rankNew Contributor
2 years ago

Hi wchiah,

Thanks for the response. In my previous message I wasn't full. My Cyclone V device has 6 trans (2 blocks with 3 transceivers). The PCIE HIP occupies 2 trans as a result there are 4 unoccupied trans.

I can compile the project there I have 1 PCIE wrapped into QSYS and 3 SGMIIs separate from QSYS as Native PHY IPs. I am trying to understand that it is impossible to have in one QSYS structure 1 PCIE and 3 SGMII as TSE (Triple-Speed Ethernet) IPs instead of 3 SGMII Native PHY IPs.

BR, Majo