Code verilog has an error

Hi everybody!

I have a code, I write it to control for 7 segment. but I did't understand that an error appearing. I repaired for many times. But cannot .............. I'm confuse.

module led (clkin_50,cpu_resetn,

seven_seg_sel[1],

seven_seg_sel[2],

seven_seg_sel[3],

seven_seg_sel[4],

seven_seg_a,

seven_seg_b,

seven_seg_c,

seven_seg_d,

seven_seg_e,

seven_seg_f,

seven_seg_g,

seven_seg_dp

);

input clkin_50, cpu_resetn;

reg [3:0] state;

reg [6:0] number;

output seven_seg_sel[1],seven_seg_sel[2],seven_seg_sel[3],seven_seg_sel[4],seven_seg_a,seven_seg_b,seven_seg_c,seven_seg_d,seven_seg_e,seven_seg_f,seven_seg_g,seven_seg_dp;

parameter number4 = 7'b1001100;

assign {seven_seg_sel[4],seven_seg_sel[3],seven_seg_sel[2], seven_seg_sel[1]} = state;

assign{seven_seg_a,seven_seg_b,seven_seg_c,seven_seg_d,seven_seg_e,seven_seg_f,seven_seg_g} = number;

assign seven_seg_dp = 1;

always @ (posedge clkin_50)

if (cpu_resetn == 0)

state <= 4'b0000;

else

state <= 4'b0001;

always @ (posedge clkin_50)

if (cpu_resetn == 0)

number <= 7'h7f;

else

number <= number4;

endmodule

I attached a photo which I took photograph.

Any help I really thanks and wait.........