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Altera_Forum
Honored Contributor
Honored ContributorCode Optimization for FPGA
I was told the multiplier "*" in the code blow will dramatically slow down the operating speed(Fmax) of FPGA. But i don't konw why. Could somebody give me some hints on it? Any idea to optimize it? ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Because you're expecting a non trivial multiply (ie non power of 2 which is simply a bit shift) and a compare to be done in a single clock cycle. Longer logic chains = slower clock speed. This is on top of the priority encode you build with all of those elseifs. You'd be much better off trying to pipeline it all somehow (not much I can say, as you are using inputs directly). On a side note - why are all your setting_* signals std_logic_vectors? why not just make them unsigned in the port map, and you'll save yourself a load of RSI. --- Quote End --- What is RSI? Could explain more on the diffence of using "std_logic_vector" and "unsinged"?
