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Honored Contributor
Honored Contributorclocks on logic analyzer
I have a pll, a NCO block on my system. I am trying to verify the design on signaltap logic analyzer. The input to the pll, is the 50 MHz on-board oscillator. I used this on board oscillator as the a...
Altera_ForumHonored Contributor
Honored ContributorSignal tap is not an ocilloscope, it is a logic analyser, so each "dot" is a single data sample. Each sample is 20ns. With a 5MHz output clock, the output clock should be high for 5 samples and low for 5 samples.
