Clocking directly vs logic "distortion"

You don't. Logic generated clocks are not recommended in fpgas.

With your pll driven clock (or direct from a crystal) you can use time quest to work out all the delays for you.

Never ever use logic clocks.

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You don't. Logic generated clocks are not recommended in fpgas.

With your pll driven clock (or direct from a crystal) you can use time quest to work out all the delays for you.

Never ever use logic clocks.

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Ok, Excellent.

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You don't. Logic generated clocks are not recommended in fpgas.

With your pll driven clock (or direct from a crystal) you can use time quest to work out all the delays for you.

Never ever use logic clocks.

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Thanks for the sharing.

I'm running into this again, and still I get this nagging feeling.

What if it's a mode register and it's a low priority burst. Wouldn't it be wasting usefull pll resources?

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I'm running into this again, and still I get this nagging feeling.

What if it's a mode register and it's a low priority burst. Wouldn't it be wasting usefull pll resources?

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Why not use a clock enable?

Ok thanks, I will look into that. "And have for a bit".

But I don't really understand. The way I visualize it, (and have modules doing sound like this) internally the data starts out at some point. And gets pushed along a chain of events, all getting the master clock from the main source. And gets toggled when a master clock derived latch tells it to toggle. And eventually if it's done within the sample period, the registers are set and i'm happy. Say if i'm shy of the time it takes to execute a function I get no results, If all the functions did execute results are gotten. Does this mean i'm trying to use the FPGA in a way, the compiler attempts to help me with? (No, but the placer likes to place and deskew it, as i knew already too) <- not my area of expertise tho, so correct me if im wrong. :D

Also, how is sending a one bit square wave along with data worse than the data being sent. Doesn't this devalue the data?

It actually answered itself, was getting late.. I should have gotten this already. :P

There's no need here to clock with logic, since it's redundant.