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Honored Contributor
Honored ContributorClocking directly vs logic "distortion"
Hi, Say you have a perfect theoretical clock source, and divide it with logic to a clock source/data chunk. How would you estimate the distortion caused by this process, given the transistor si...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I'm running into this again, and still I get this nagging feeling. What if it's a mode register and it's a low priority burst. Wouldn't it be wasting usefull pll resources? --- Quote End --- Why not use a clock enable?
