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Altera_Forum's avatar
Altera_Forum
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10 years ago

Clocking directly vs logic "distortion"

Hi, Say you have a perfect theoretical clock source, and divide it with logic to a clock source/data chunk. How would you estimate the distortion caused by this process, given the transistor si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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I'm running into this again, and still I get this nagging feeling.

What if it's a mode register and it's a low priority burst. Wouldn't it be wasting usefull pll resources?

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Why not use a clock enable?