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Altera_Forum
Honored Contributor
Honored ContributorClocking directly vs logic "distortion"
Hi, Say you have a perfect theoretical clock source, and divide it with logic to a clock source/data chunk. How would you estimate the distortion caused by this process, given the transistor si...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You don't. Logic generated clocks are not recommended in fpgas. With your pll driven clock (or direct from a crystal) you can use time quest to work out all the delays for you. Never ever use logic clocks. --- Quote End --- Ok, Excellent.
