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roeekalinsky's avatar
roeekalinsky
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5 years ago

Clock synthesis and de-skewing using an IOPLL in Arria 10

I'm trying unsuccessfully to use an IOPLL to synthesize a clock and have it be in-phase with the reference clock, where both the reference clock and the synthesized clock are routed on GCLKs. By "in-...
dlevit's avatar
dlevit
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4 years ago

Thank you for the detailed answer!

I appreciate your insight. I need to cross signals from the upstream to the downstream clock domain, but the frequency is rather low, and your method looks very promising.

Thanks,

Dima

roeekalinsky's avatar
roeekalinsky
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4 years ago

You're welcome. Good luck!

-Roee