Forum Discussion
roeekalinsky
Contributor
ContributorClock synthesis and de-skewing using an IOPLL in Arria 10
I'm trying unsuccessfully to use an IOPLL to synthesize a clock and have it be in-phase with the reference clock, where both the reference clock and the synthesized clock are routed on GCLKs. By "in-...
Ash_R_Altera
Regular Contributor
Regular ContributorApologies for that statement. You are right, the IOPLL does try to compensate from pin to pll path. Please refer below link:
Intel® Quartus® Prime Pro Edition Help version 21.1 - PLL Compensation Mode logic option
Regards
