Contributor
ContributorHi @Ash_R_Intel, thank you for your response.
Your description of normal mode matches what I thought it should do, and yes, I can confirm via the technology viewer that it is in fact implementing the feedback path exactly as you described. So it should be able to de-skew as intended, but it doesn't seem to. I say this based on the clock skew shown in the static timing analysis report.
Pasted below is a snippet from the .sta.rpt from a trivial design example showing a reg-to-reg timing path going from the "clk2" domain (the output clock from the IOPLL) to the "clk1" domain (the input clock to the IOPLL). As you can see in the report, the clock path is mapped as expected, with "clk1" on CLKCTRL_2I_G_I7, which then goes to the IOPLL, then to "clk2" on CLKCTRL_3C_G_I21 (and the IOPLL's feedback path is not explicitly shown in this report but is confirmed via technology view to be exactly as you described).
Now, as you can see in the report, there is a massive hold violation (-4.661ns) resulting from a massive skew between these two clocks (5.084ns). And we can see in the report there is a compensation delay being applied in the IOPLL (-9.485ns, shown as type "COMP"), but it isn't obvious to me how it's coming up with that compensation amount, as this is not having a de-skewing effect. Rather, it actually seems to be far too large of an "anti-delay".
Path #1: Hold slack is -4.661 (VIOLATED)
===============================================================================
+---------------------------------------------------------+
; Path Summary ;
+---------------------------------+-----------------------+
; Property ; Value ;
+---------------------------------+-----------------------+
; From Node ; ff3 ;
; To Node ; ff4 ;
; Launch Clock ; clk1 ;
; Latch Clock ; clk1 ;
; Data Arrival Time ; -0.543 ;
; Data Required Time ; 4.118 ;
; Slack ; -4.661 (VIOLATED) ;
; Worst-Case Operating Conditions ; Slow 900mV -40C Model ;
+---------------------------------+-----------------------+
+-------------------------------------------------------------------------------------+
; Statistics ;
+------------------------+-------+-------+-------------+------------+--------+--------+
; Property ; Value ; Count ; Total Delay ; % of Total ; Min ; Max ;
+------------------------+-------+-------+-------------+------------+--------+--------+
; Hold Relationship ; 0.000 ; ; ; ; ; ;
; Clock Skew ; 5.084 ; ; ; ; ; ;
; Data Delay ; 0.787 ; ; ; ; ; ;
; Number of Logic Levels ; ; 0 ; ; ; ; ;
; Physical Delays ; ; ; ; ; ; ;
; Arrival Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; IC ; ; 5 ; 4.989 ; 61 ; 0.000 ; 2.573 ;
; Cell ; ; 9 ; 3.166 ; 39 ; 0.000 ; 0.804 ;
; PLL Compensation ; ; 1 ; -9.485 ; 0 ; -9.485 ; -9.485 ;
; Data ; ; ; ; ; ; ;
; IC ; ; 1 ; 0.529 ; 67 ; 0.529 ; 0.529 ;
; Cell ; ; 2 ; 0.086 ; 11 ; 0.000 ; 0.086 ;
; uTco ; ; 1 ; 0.172 ; 22 ; 0.172 ; 0.172 ;
; Required Path ; ; ; ; ; ; ;
; Clock ; ; ; ; ; ; ;
; IC ; ; 3 ; 2.587 ; 66 ; 0.000 ; 2.587 ;
; Cell ; ; 4 ; 1.321 ; 34 ; 0.000 ; 0.632 ;
+------------------------+-------+-------+-------------+------------+--------+--------+
Note: Negative delays are omitted from totals when calculating percentages
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Arrival Path ;
+----------+----------+----+--------+--------+---------------------+------------+---------------------------------------------------------------------------------------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ;
+----------+----------+----+--------+--------+---------------------+------------+---------------------------------------------------------------------------------------------------+
; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ;
; 0.000 ; 0.000 ; ; borrow ; ; ; ; time borrowed ;
; -1.330 ; -1.330 ; ; ; ; ; ; clock path ;
; 0.000 ; 0.000 ; ; ; ; ; ; source latency ;
; 0.000 ; 0.000 ; ; ; 1 ; PIN_AR36 ; ; clk1_p ;
; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y115_N47 ; ; clk1_p~input|i ;
; 0.632 ; 0.632 ; RR ; CELL ; 1 ; IOIBUF_X78_Y115_N47 ; ; clk1_p~input|o ;
; 0.762 ; 0.130 ; RR ; CELL ; 1 ; IOIBUF_X78_Y115_N47 ; ; clk1_p~input~io_48_lvds_tile/ioclkin[2] ;
; 0.762 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2I_G_I7 ; ; altclkctrl_ip_01_i|altclkctrl_0|altclkctrl_ip_01_altclkctrl_2000_dpnsueq_sub_component|sd1|inclk ;
; 1.211 ; 0.449 ; RR ; CELL ; 5 ; CLKCTRL_2I_G_I7 ; ; altclkctrl_ip_01_i|altclkctrl_0|altclkctrl_ip_01_altclkctrl_2000_dpnsueq_sub_component|sd1|outclk ;
; 3.784 ; 2.573 ; RR ; IC ; 1 ; IOPLL_3C ; High Speed ; iopll_ip_01_i|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0] ;
; 4.526 ; 0.742 ; RR ; CELL ; 1 ; IOPLL_3C ; ; iopll_ip_01_i|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst~vco_refclk ;
; 4.526 ; 0.000 ; RR ; CELL ; 1 ; IOPLL_3C ; ; iopll_ip_01_i|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst~vctrl ;
; -4.959 ; -9.485 ; RR ; COMP ; 2 ; IOPLL_3C ; ; iopll_ip_01_i|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst~vcoph[0] ;
; -4.155 ; 0.804 ; RR ; CELL ; 1 ; IOPLL_3C ; ; iopll_ip_01_i|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0] ;
; -4.155 ; 0.000 ; RR ; CELL ; 1 ; IOPLL_3C ; ; iopll_ip_01_i|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst~io_48_lvds_tile/pllcout[4] ;
; -4.155 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_3C_G_I21 ; ; iopll_ip_01_i|iopll_0|altera_iopll_i|twentynm_pll|outclk[0]~CLKENA0|inclk ;
; -3.746 ; 0.409 ; RR ; CELL ; 1 ; CLKCTRL_3C_G_I21 ; ; iopll_ip_01_i|iopll_0|altera_iopll_i|twentynm_pll|outclk[0]~CLKENA0|outclk ;
; -1.330 ; 2.416 ; RR ; IC ; 1 ; FF_X77_Y121_N55 ; High Speed ; ff3|clk ;
; -1.330 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y121_N55 ; High Speed ; ff3 ;
; -0.543 ; 0.787 ; ; ; ; ; ; data path ;
; -1.158 ; 0.172 ; FF ; uTco ; 1 ; FF_X77_Y121_N55 ; ; ff3|q ;
; -1.072 ; 0.086 ; FF ; CELL ; 1 ; FF_X77_Y121_N55 ; High Speed ; ff3~la_lab/laboutb[16] ;
; -0.543 ; 0.529 ; FF ; IC ; 1 ; FF_X77_Y121_N53 ; High Speed ; ff4|asdata ;
; -0.543 ; 0.000 ; FF ; CELL ; 1 ; FF_X77_Y121_N53 ; High Speed ; ff4 ;
+----------+----------+----+--------+--------+---------------------+------------+---------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Required Path ;
+---------+----------+----+--------+--------+---------------------+------------+---------------------------------------------------------------------------------------------------+
; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ;
+---------+----------+----+--------+--------+---------------------+------------+---------------------------------------------------------------------------------------------------+
; 0.000 ; 0.000 ; ; ; ; ; ; latch edge time ;
; 0.000 ; 0.000 ; ; borrow ; ; ; ; time borrowed ;
; 3.754 ; 3.754 ; ; ; ; ; ; clock path ;
; 0.000 ; 0.000 ; ; ; ; ; ; source latency ;
; 0.000 ; 0.000 ; ; ; 1 ; PIN_AR36 ; ; clk1_p ;
; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X78_Y115_N47 ; ; clk1_p~input|i ;
; 0.632 ; 0.632 ; RR ; CELL ; 1 ; IOIBUF_X78_Y115_N47 ; ; clk1_p~input|o ;
; 0.791 ; 0.159 ; RR ; CELL ; 1 ; IOIBUF_X78_Y115_N47 ; ; clk1_p~input~io_48_lvds_tile/ioclkin[2] ;
; 0.791 ; 0.000 ; RR ; IC ; 2 ; CLKCTRL_2I_G_I7 ; ; altclkctrl_ip_01_i|altclkctrl_0|altclkctrl_ip_01_altclkctrl_2000_dpnsueq_sub_component|sd1|inclk ;
; 1.321 ; 0.530 ; RR ; CELL ; 5 ; CLKCTRL_2I_G_I7 ; ; altclkctrl_ip_01_i|altclkctrl_0|altclkctrl_ip_01_altclkctrl_2000_dpnsueq_sub_component|sd1|outclk ;
; 3.908 ; 2.587 ; RR ; IC ; 1 ; FF_X77_Y121_N53 ; High Speed ; ff4|clk ;
; 3.908 ; 0.000 ; RR ; CELL ; 1 ; FF_X77_Y121_N53 ; High Speed ; ff4 ;
; 3.754 ; -0.154 ; ; ; ; ; ; clock pessimism removed ;
; 3.754 ; 0.000 ; ; ; ; ; ; clock uncertainty ;
; 4.118 ; 0.364 ; ; uTh ; 1 ; FF_X77_Y121_N53 ; ; ff4 ;
+---------+----------+----+--------+--------+---------------------+------------+---------------------------------------------------------------------------------------------------+
----------------------------
; Extra Fitter Information ;
----------------------------
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