Contributor
ContributorThanks, @sstrell, but zero delay buffer mode doesn't seem to be what I need. That's for putting out a clock to the board via a chip level I/O pin, and de-skews the clock for that external output, not for an internal GCLK.
From that doc (UG-01155), which I have been scouring:
"If you select the zero delay buffer mode, the PLL must feed an external clock output pin and compensate for the delay introduced by that pin. The signal observed on the pin is synchronized to the input clock. The PLL clock output connects to the altbidir port and drives zdbfbclk as an output port. If the PLL also drives the internal clock network, a corresponding phase shift of that network occurs."
My situation is purely on-chip, no external I/O involved. Assume I have a given clock signal "clk1" that's already on a GCLK, and I need to produce another clock signal "clk2" that is also on a GCLK, is at an integer multiple of the frequency of "clk1", and is phase-aligned with "clk1". That's what I'm trying to accomplish.
It seems like in principle what I need is more analogous to the IOPLL's "external mode", which exposes the feedback path to the user. Except that instead of running the feedback path off-chip through I/O pins, I need to run the feedback path on-chip through just a clock control block and GCLK. But "external mode" doesn't allow that either, it already has the input pin and output pin I/O buffers built in and has to go off-chip. So...?
