Forum Discussion
roeekalinsky
Contributor
ContributorClock synthesis and de-skewing using an IOPLL in Arria 10
I'm trying unsuccessfully to use an IOPLL to synthesize a clock and have it be in-phase with the reference clock, where both the reference clock and the synthesized clock are routed on GCLKs. By "in-...
sstrell
Super Contributor
Super ContributorI think you may be using the wrong mode. See the user guide:
Maybe you want to be using zero-delay buffer mode? It's not entirely clear what your goal is so I'm kind of guessing.
