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Altera_Forum's avatar
Altera_Forum
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16 years ago

clock synchronization

I'm currently using a PPL to generate 120MHz ADC clock, and this clock should be aligned with a pulse (denoted as "pulse") falling edge when the synchronization signal (denoted as "SYNC") is high. Bo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The issue of enabling the PLL at pulse falling edge is not going to work because the PLL needs time to lock. I wonder if you can do it at all with a simple PLL. You will need to think of how to lock the pulse with your 120 clk in some sort of feedback loop(altera PLL may have feedback inputs, never used them)