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Altera_Forum's avatar
Altera_Forum
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16 years ago

clock synchronization

I'm currently using a PPL to generate 120MHz ADC clock, and this clock should be aligned with a pulse (denoted as "pulse") falling edge when the synchronization signal (denoted as "SYNC") is high. Bo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The problem rest on that the ADC clock should be aligned with the "pulse"; that is, their falling edge should show up at the same time for each period of the "pulse" when the "SYNC" is active. I'm considering to let the rising edge of the "SYNC" reset the PLL and then the falling edge of the "pulse" should enable the PLL. However, I don't know how to implement it? :(