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Altera_Forum's avatar
Altera_Forum
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17 years ago

clock synchronization

I'm currently using a PPL to generate 120MHz ADC clock, and this clock should be aligned with a pulse (denoted as "pulse") falling edge when the synchronization signal (denoted as "SYNC") is high. Bo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You may want to clarify your specification for aligned in terms of phase deviation. Can we assume, that the sync pulse is phase locked to your primary clock source? Also, can you accept a alignment duration of multiple sync periods?

Depending on some specification details, the design isn't necessarily feasible, I think.