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Honored Contributor
Honored Contributorclock structure?
The cyclone ii fpga handbook says it has 4 built in PLLs. Are these associated with a particular input pin on the device? Is one of the main advantages of using a PLL on a clock input to increase acc...
Altera_ForumHonored Contributor
Honored ContributorYes, you may have trouble achieving timming closure with that.
If possible, use one of the dedicated clock input pins. The general I/O pins can't drive the global (low skew) clock networks directly, so the clock signal will be distributed using the generic fabric, which will lead to high skew. This can be somewhat remedied by insering a LCELL primitive between the clock signal from the pin and the clock signal actually used to drive the logic within the FPGA -- the output of the LCELL can be routed though a global clock network. This mostly fixes the problem for the logic within the FPGA. But even so, due to the delay between the I/O pin and the LCELL output, it can be difficult to achieve I/O timming closure.
