clock structure?

Please consult the devive manual. The clock managment chapter is answering your question in detail (at least most of it).

As a brief answer, each PLL has associated clock inputs. With Cyclone II, a PLL must be exclusively clocked by one of it's associated inputs. So feeding an external clock to only one input implies, that you can only use one PLL in the design. This restriction has been removed with successor chips.

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Is one of the main advantages of using a PLL on a clock input to increase accuracy in a system with noise?

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Not particularly. It's intended for clock synthesis, mainly generation of high clock frequencies and multiple phase locked clocks. They are needed e.g. for DDR RAM controllers or high speed serial interfaces. But PLL's rather increase the device susceptibility to noise than making it operating more reliable. The analog PLL supply of Cyclone II (VCCA) must be carefully bypassed to avoid problems of PLL loose of lock in presence of supply interferences. Also the clock signal quality is more critical when using PLLs.