Clock skews, enables and timing

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When I look at the compile window it gives me errors such as gated clocks causing skew...

Someone mentioned on here that I need to use chip enable clocks to sort out the gated clock issue but I do not know how to do this?

could someone give me some pointers in verilog?

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See http://www.alteraforum.com/forum/showthread.php?t=2388. That thread goes into detail about design recommendations for gated clocks. One of the posts talks about clock enables and has a reference to the Quartus text editor templates showing the proper way to code for clock enables.