Clock Skew Issue

Why are you doing a ring oscillator? If you're trying to make a lower speed clock, use a PLL or a clock enable. A ring oscillator is going to have a lot of variation. Data delays can vary over PVT by quite a bit, let's say 50%. That means your oscillator's frequency can vary by 50%. That's generally not very useful.

As for clock skew, if the final clock output of your ring oscillator gets onto a global, then the actual skew to all the destinations will be negligible. In fact, if it doesn't get on a global, the actual skew is not going to be a problem, at least as far as everything it's driving. But if there are any paths who transfer data between this ring oscillator's clock and a clock that is not created by logic, then you will have large amounts of skew. You've basically added a large delay to your clock line, so it is out of whack(i.e. skew) with any other domains it might have to interface with.