Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

clock recovery stratix IV GX edition

does anyone know that the FPGA(stratix IV GX edition) allows to turn the CDR (clock data recovery ) off
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Dierckx,

I am starting a design using Transceivers in a Stx IV Device. The first step of the design consists in interfacing a high-speed ADC (2Gbps) to the Stx IV receiver blocks.

Physically, these 2 chips are close to each other (4 inches differential line length at max) thus signal integrity should not be an issue (compared to a data transmission over a backplane). In these conditions, I am wondering whether I should operate the CDR of the receivers in LTR, LTD or Automatic Lock mode ! :confused:

What is your opinion (advantages/drawbacks) about these different modes ? Have you experienced all of them ? What's your reason for using LTR mode only ?

Thank You !

Olivier