clock recovery stratix IV GX edition

I already found the solution in the manual:D :

lock-to-reference mode

In LTR mode, the phase frequency detector in the CDR tracks the receiver input reference clock,

rx_cruclk. The PFD controls the charge pump that tunes the VCO in the CDR. Depending on the data rate and the selected input reference clock frequency, the Quartus II software automatically selects the appropriate /M and /L

divider values such that the CDR output clock frequency is half the data rate. An active high, the rx_pll_locked status signal is asserted to indicate that the CDR has locked to phase and frequency of the receiver input reference clock.

thanks anyway

Hi Dierckx,

I am starting a design using Transceivers in a Stx IV Device. The first step of the design consists in interfacing a high-speed ADC (2Gbps) to the Stx IV receiver blocks.

Physically, these 2 chips are close to each other (4 inches differential line length at max) thus signal integrity should not be an issue (compared to a data transmission over a backplane). In these conditions, I am wondering whether I should operate the CDR of the receivers in LTR, LTD or Automatic Lock mode ! :confused:

What is your opinion (advantages/drawbacks) about these different modes ? Have you experienced all of them ? What's your reason for using LTR mode only ?

Thank You !

Olivier