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Altera_Forum
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16 years ago

clock recovery stratix IV GX edition

does anyone know that the FPGA(stratix IV GX edition) allows to turn the CDR (clock data recovery ) off
Altera_Forum's avatar
Altera_Forum
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16 years ago

I already found the solution in the manual:D :

lock-to-reference mode

In LTR mode, the phase frequency detector in the CDR tracks the receiver input reference clock,

rx_cruclk. The PFD controls the charge pump that tunes the VCO in the CDR. Depending on the data rate and the selected input reference clock frequency, the Quartus II software automatically selects the appropriate /M and /L

divider values such that the CDR output clock frequency is half the data rate. An active high, the rx_pll_locked status signal is asserted to indicate that the CDR has locked to phase and frequency of the receiver input reference clock.

thanks anyway