Clock problem

Hi All,

I am trying to reduce the clock frequency from 25 MHZ to 12.5 MHZ using VHDL. I also intend to implement this in hardware, however I am having a lot of difficulty with my code. I can not assign a new clock frequency to an output variable which I wanted to assign to an output pin.

I am getting the following error for my code which is shown below:

Error (10517): VHDL type mismatch error at clock.vhd(23): std_logic_vector type does not match integer literal

My Code:

-- Divide clock frequency by 2

-- Standard libary delarations

library ieee;

use ieee.std_logic_1164.all;

-- define input and outputs for the entity

entity clock is port(

clk_in: in std_logic;

clk_out: buffer std_logic;

va: buffer std_logic_vector(2 downto 0) );

end clock;

-- internal function of enetity

architecture behave of clock is

--internal variable

signal count : integer :=1;

begin

process (clk_in,clk_out,va)

begin

-- Required in order to convert the sinewave to a square wave

clk_out <= not clk_in;

-- Check for rising edge of clock

if(clk_out'event and clk_out='1') then

--increment the count variable by 1

count <=count+1;

-- when count is 2

if(count = 2) then

--assign 1 to the variable which will be assigned to an output pin

va <= 1;

end if;

end if;

end process;

end behave;

Thank you in advance.