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Altera_Forum's avatar
Altera_Forum
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14 years ago

Clock problem

Hi All, I am trying to reduce the clock frequency from 25 MHZ to 12.5 MHZ using VHDL. I also intend to implement this in hardware, however I am having a lot of difficulty with my c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Gated clocks are bad.

but anyway, what's the point of using signal va as std_logic_vector? You're assigning one bit value to 3bit bus. Also the code logically won't work, since You don't reset the counter.