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Altera_Forum
Honored Contributor
14 years agoClock problem
Hi All, I am trying to reduce the clock frequency from 25 MHZ to 12.5 MHZ using VHDL. I also intend to implement this in hardware, however I am having a lot of difficulty with my c...
Altera_Forum
Honored Contributor
14 years agoI can't understand what you are trying to do.
From your first sentence I assumed you want clk_out to be half the frequency of clk_in. This can be done with simple code, like this: if(clk_in'event and clk_in='1') then clk_out <= not clk_out; end if; Regarding the error. that's normal if you write va <= 1 You defined va as a std_logic vector 3 bits long, so you must use va <= "000" Anyway, your code seems to be useless since va is not initialized to any other value and assigned only to 1 when count is 2. I'd expect at least a reset signal, in order to reset count and va to initial status.